This invention relates generally to digital circuits for regenerating a jittered clock signal. More particularly, this invention relates to a dejitter circuit which receives a jittered telecommunications signal, and which uses a clock source of higher frequency for regenerating the telecommunications signal at the rate of the incoming telecommunications signal.
DS0, DS1, DS2, and DS3 telecommunications signals are well defined according to CCITT specifications. Essentially,, a DS0 signal is a signal having a bit rate of 64 Kbits/sec. DS1 signal is comprised of twenty-four DS0 segments plus overhead for a total bit rate of 1.544 Mbits/sec (plus or minus approximately 200 b/sec). In turn, four DS1 signals plus some overhead (bit stuffing) constitute a 6.312 Mb/sec DS2 signal, and four DS2 signals plus some additional overhead constitutes a 44.736 Mb/sec DS3 signal.
DS3 signals are commonly used between central offices for high speed communication. When the DS3 signal is received, it is often demultiplexed into its seven composite DS2 signals, with the bit stuffing utilized for control and essentially removed from the DS2 signals. In turn, the DS2 signals are often demultiplexed into their four composite DS1 signals with the DS2 bit stuffing utilized for control and essentially removed from the resulting DS1 signals. Each resulting DS1 signal has a bit rate of approximately 1.544 Mb/sec plus or minus 200 b/sec. However, because in generating the DS1 signal the overhead or stuffing bits are removed, the bit stream of the DS1 signal is gapped or "jittered". Additional jitter termed "transport" or "systematic" jitter is also found in the DS1 signal due to the fact that all systems introduce noise into the signals which they are carryinq. Jitter is undesirable as it can introduce error in the decoding of the signal.
With the advent of the optical network, additional telecommunication signals have been defined according to CCITT specifications. The basic SONET signal is an STS-1 signal having a bit rate of 51.84 Mb/sec. An STS-3 signal (155.52 Mb/sec) has three times the bit rate of the STS-1 signal. Often the STS-1 or STS-3 signals are used to carry the data payloads of DS0, DS1, DS2 and DS3 signals. In fact, the STS signals can also be required to carry the data payload of standard European signals such as a 2.048 Mb/sec signal.
Standard devices such as phase locked loops are known in the art for tracking signal rates and for generating a clock of the nominal received rate for eliminating jitter. Phase locked loops however, have several drawbacks including expense and the requirement of analog implementation. The subject invention eliminates the need for a phase locked loop through the use of a small amount of digital circuitry capable of implementation on a small section of an LSI circuit.